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DATA BULLETIN
MX604
FEATURES
1200bps forward, 75bps back channels Conforms to relevant sections of v.23 and ETSI specifications Line Equalization 1200bps Data Retiming Facility can eliminate external UART Low Voltage Operation (3.3 to 5.0V)
v.23 Compatible Modem
PRELIMINARY INFORMATION
APPLICATIONS
Low Power Operation 1mA typ. @ 3.3V Operating Mode 1A typ. Zero-Power Mode Standard 3.58Mhz Xtal/Clock Telephone Telemetry System Applications
Status
Telephone Line
Line Interface
Control
MX604
Data
C
The MX604 is a low voltage, low power CMOS device, used for the reception or transmission of asynchronous 1200bps data and full-duplex 75bps back channel data in accordance with CCITT V.23 and ETSI specifications. This device provides an optional Tx and Rx data retiming function which can eliminate, based on user preference, the need for an external UART when operating at 1200bps. The device can disable the back channel or be operated so only the mark or space tone is produced. The optional line equalizer is incorporated into the receive path and is controlled by an external logic level. The MX604 may be used in a wide range of telephone telemetry systems. Low voltage capability, a low operating current (1mA typ. @ VDD = 3.3V), and a very low current 'sleep' mode (1A typ.) make the MX604 ideal for both portable terminal and line powered applications. The MX604 is available in the following packages: 24-pin TSSOP (MX604TN), 16-pin SOIC (MX604DW) and 16-pin PDIP (MX604P).
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
2
MX604 PRELIMINARY INFORMATION
CONTENTS
Section 1. 2. 3. 4. Page
Block Diagram .......................................................................................................... 3 Signal List ................................................................................................................. 4 External Components .............................................................................................. 5 General Description ................................................................................................. 5
4.1 Xtal Osc and Clock Dividers ................................................................................................... 5 4.2 Mode Control Logic ................................................................................................................ 6 4.3 Rx Input Amplifier ................................................................................................................... 6 4.4 Receive Filter and Equalizer................................................................................................... 6 4.5 Energy Detector...................................................................................................................... 7 4.6 FSK Demodulator ................................................................................................................... 7 4.7 FSK Modulator and Transmit Filter......................................................................................... 7 4.8 Rx Data Retiming ................................................................................................................... 9 4.9 Tx Data Retiming.................................................................................................................. 10
5.
Application .............................................................................................................. 11
5.1 Line Interface........................................................................................................................ 11
6.
Performance Specification .................................................................................... 12
6.1 Electrical Performance ......................................................................................................... 12 6.2 Timing................................................................................................................................... 15 6.3 Packaging............................................................................................................................. 16
MXCOM, Inc. reserves the right to change specifications at any time and without notice
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
3
MX604 PRELIMINARY INFORMATION
1.
Block Diagram
XTAL/ CLOCK XTAL VDD VBIAS VSS RXAMPOUT RXIN
Xtal Osc and Clock Dividers Energy Detect Mode Control Logic Receive Filter and Equalizer VBIAS FSK De-modulator Rx/Tx Data Re-timing Transmit Filter and Output Buffer FSK Modulator
RXEQ DET M1 M0 RXD CLK RDY TXD
TXOUT
Figure 1: Block Diagram
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
4
MX604 PRELIMINARY INFORMATION
2.
Signal List
Pin No. Name TN 1 2 5 6 7 8 11 12 13 XTAL XTAL/CLOCK M0 M1 RXIN RXAMPOUT TXOUT VSS VBIAS output input input input input output output power output Output of the on-chip Xtal oscillator inverter. Input to the on-chip Xtal oscillator inverter. A logic level input for setting the mode of the device. See section 4.2 A logic level input for setting the mode of the device. See section 4.2 Input to the Rx input amplifier. Output of the Rx input amplifier. Output of the FSK generator. Negative supply (ground). Internally generated bias voltage, held at VDD /2 when the device is not in 'Zero-Power' mode. Should be decoupled to VSS by a capacitor mounted close to the device pins. A logic level input for enabling/disabling the equalizer in the receive filter. See section 4.4 A logic level input for either the raw input to the FSK Modulator or data to be re-timed depending on the state of the M0, M1 and CLK inputs. See section 4.9 A logic level input which may be used to clock data bits in/out of the FSK Data Retiming block. A logic level output carrying either the raw output of the FSK Demodulator or re-timed characters depending on the state of the M0, M1 and CLK inputs. See section 4.8 A logic level output of the on-chip energy detect circuit. "Ready for data transfer" output of the on-chip data retiming circuit. This open-drain active low output may be used as an Interrupt Request/Wake-up input to the associated C. An external pull-up resistor should be connected between this output and VDD. The positive supply rail. Levels and thresholds within the device are proportional to this voltage. Should be decoupled to VSS by a capacitor mounted close to the device pins. No internal connections Type Description
P, DW 1 2 3 4 5 6 7 8 9
10 11
14 17
RXEQ TXD
input input
12 13
18 19
CLK RXD
input output
14 15
20 23
DET
RDY
output output
16
24
VDD
power
3, 4, 9, 10 ,15, 16, 21, 22
N/C
This device is capable of detecting and decoding small amplitude signals. Achieving the VDD and VBIAS decoupling and protection of the receive path from extraneous in-band signals is very important. It is recommended that decoupling capacitors be placed so the connection between them and the device pins is as short as possible. A ground plane protecting the receive path will help attenuate interfering signals.
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
5
MX604 PRELIMINARY INFORMATION
3.
External Components
VDD C1
X1
C2
XTAL
1 2 3 4 5 6 7 8
16 15 14
VDD RDY DET RXD CLK TXD RXEQ VBIAS
R1
C3
XTAL/CLOCK
M0 From C M1 RXIN RXAMPOUT TXOUT VSS
MX604
13 12 11 10 9
C4
5%, 10% 10% 10%
R1 C1, C2 C3 C4 X1 Note 1
100k 18pF 0.1F 0.1F 3.579545MHz
Figure 2: Recommended External Components for Typical Application External Components Notes: 1. A crystal frequency of 3.579545MHz 0.1% is required for correct FSK operation. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V DD, peak-peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. Operation of this device without a Xtal or Clock input may cause device damage.
4.
4.1
General Description
Xtal Osc and Clock Dividers
Frequency and timing accuracy of the MX604 is determined by a 3.579545MHz clock present at the XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components C1, C2 and X1 of Figure 2, or it may be supplied from an external source to the XTAL/CLOCK input. If supplied from an external source, C1, C2 and X1 should not be used. The on-chip oscillator is disabled in the 'Zero-Power' mode. If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must be set when the clock is not available. Failure to observe this rule may cause a significant rise in the supply current drawn by MX604 as well as generating undefined states of the RXD, DET and RDY outputs.
1998 MXCOM, INC. Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
To/From C
v.23 Compatible Modem
6
MX604 PRELIMINARY INFORMATION
4.2
Mode Control Logic
M1 0 0 1 1 M0 0 1 0 1 [1] If enabled. Rx Mode 1200bps off 1200bps 'Zero-Power' Tx Mode 75bps 1200bps off Data Retime[1] Rx Tx Rx -
The MX604's operating mode is determined by the logic levels applied to the M0 and M1 input pins:
Note: On applying power to the device the mode must be set to 'ZP', i.e. M0=1, M1=1, until VDD has stabilized. In the 'Zero-Power' mode, power is removed from all internal circuitry. When leaving 'Zero-Power' mode there must be a 20ms delay before any Tx data is passed to, or Rx data read from, the device to allow the bias level, filters and oscillator to stabilize.
4.3
Rx Input Amplifier
The Rx Input Amplifier is used to adjust the signal received to the correct amplitude for the FSK receiver and Energy Detect circuits (see section 5.1).
4.4
Receive Filter and Equalizer
The Receive Filter and Equalizer is used to attenuate out of band noise and interfering signals, especially the locally generated 75bps transmit tones which might otherwise reach the 1200bps FSK Demodulator and Energy Detector circuits. This block also includes a switchable equalizer section. When the RXEQ pin is low the overall group delay of the receive filter is flat over the 1200bps frequency range. If the RXEQ pin is high the receive filter's typical overall group delay will be as shown in Figure 3.
0.025 Delay/ms 0
-0.025 -0.05 -0.075 -0.1 -0.125 -0.15 500
1000
1500 Frequency/Hz
2000
2500
Figure 3: Rx Equalizer Group Delay (RXEQ = 1) with respect to 1700Hz
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
7
MX604 PRELIMINARY INFORMATION
4.5
Energy Detector
The Energy Detector block operates by measuring the level of the signal at the output of the Receive Filter, and comparing it against a preset threshold. The DET output will be set high when the level has exceeded the threshold for a sufficient time. Amplitude and time hysteresis are used to reduce chattering of the DET output in marginal conditions. Note: This circuit may also respond to non-FSK signals such as speech.
Line Signal DET M0, M1
TeON
FSK signal TeOFF
FSK Receive mode
See section 6.1 for definitions of TeON and TeOFF
Figure 4: FSK Level Detector Operation
4.6
FSK Demodulator
The FSK Demodulator block converts the 1200bps FSK input signal to a logic level received data signal which is output via the RXD pin as long as the Data Retiming function is not enabled (see section 4.8). This output does not depend on the state of the DET output. When the Rx 1200bps mode is 'off' or in 'ZP' the DET and RXD pins are held low. Note: In the absence of a valid FSK signal, the demodulator may falsely interpret speech or other extraneous signals as data. For this reason it is advised that the RXD pin be read only when data is expected.
4.7
FSK Modulator and Transmit Filter
The FSK Modulator and Transmit Filter blocks produce a tone according to the TXD, M0 and M1 inputs as shown in the table below, assuming data retiming is not being used: M1 1 1 0 0 FSK Modulator and Transmit Filter Note: [1] TXOUT held at approx. VDD/2. When modulated at the appropriate baud rates, the Transmit Filter and associated external components (see section 5.1) limit the FSK out of band energy sent to the line in accordance with Figure 5 and Figure 6, assuming that the signal on the line is at -6dBm or less. M0 1 0 0 1 450Hz 2100Hz TXD = 0 0Hz[1] 390Hz 1300Hz TXD = 1
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
0 dBm -10
8
MX604 PRELIMINARY INFORMATION
-20
3400 Hz
-30
1300 Hz
-40
-50
-60
28 kHz
-70 10 100 1000 10000 Frequency/ Hz 100000
Figure 5: Tx limits at 75bps rate
0 dBm
-10
-20
-30
450 Hz -40 3400 Hz
-50
-60 28 kHz
-70 10 100 1000 10000 Frequency / Hz 100000
Figure 6: Tx limits at 1200bps rate
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
9
MX604 PRELIMINARY INFORMATION
4.8
Rx Data Retiming
The Rx Data Retiming function may be used when the received data consists of 1200bps asynchronous characters, each character consisting of one start bit followed by a minimum of 9 formatted bits as shown in the table below. Data bits 7 7 8 8 9 Parity bits 0 1 0 1 0 Stop bits 2 1 1 1 1
When enabled in receive mode, the Data Retiming block extracts the first 9 bits of each character following the start bit, from the received asynchronous data stream, and presents them to the C, under the control of strobe pulses applied to the CLK input. The timing of these pulses is not critical. They may be generated easily by a simple software loop. This facility removes the need for a UART in the C without incurring an excessive software overhead. The receive retiming block consists of two 9-bit shift registers, the input of the first is connected to the output of the FSK demodulator and the output of the second is connected to the RXD pin. The first register is clocked by an internally generated signal that stores the 9 received bits following the timing reference of a high to low transition at the output of the FSK demodulator. When the 9th bit is clocked into the first register these 9 bits are transferred to the second register, a new stop-start search is initiated and the CLK input is sampled. If the CLK input is low at this time the RDY pin is pulled low and the first received bit is output on the RXD pin. The CLK pin should then be pulsed high 9 times, the first 8 high to low transitions will be used by the device to clock out the bits in the second register. The RDY output is cleared the first time the CLK input goes high. At the end of the 9th pulse the RXD pin will be connected to the FSK demodulator output. To use the Data Retiming function, the CLK input should be kept low until the RDY output goes low; if the Data Retiming function is not required then the CLK input should be kept high at all times. The only restrictions on the timing of the CLK waveform are those shown in Figure 7 and the need to complete the transfer of all nine bits into the C within the time of a complete character at 1200bps.
FSK Demod output :
9 Bits of data
START 1 2
Received Character 'n' 3 4 5 6 7 8 9 STOP
RDY output : RXCK input : RXD output :
1 9
Retimed data bits from received character 'n'
RDY
tD tcLO tcHI
RXCK
tD tD
Data Bit 1 Data Bit 2
RXD
tD = Internal MX604 delay, tcHI = CLK high time, tcLO = CLK low time
Figure 7: FSK Operation with Rx Data Re-timing Note: If enabled, the Data Retiming block may interpret speech or other signals as random characters.
1998 MXCOM, INC. Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
10
MX604 PRELIMINARY INFORMATION
If the Data Retiming facility is not required, the CLK input to the MX604 should be kept high at all times. The asynchronous data from the FSK Demodulator will then be connected directly to the RXD output pin, and the RDY output will not be activated by the FSK signal. This case is illustrated by the example in Figure 8
Received Character 'n'
FSK Demod output : RXD output :
START START
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
STOP STOP
Figure 8: FSK Operation without Rx Data Re-timing (CLK always high)
4.9
Tx Data Retiming
The Tx Data Retiming block, when enabled in 1200bps transmit mode, requires the controlling C to load 1 bit at a time into the device by a pulse applied to the CLK input. The timing of this pulse is not critical. It may be generated easily by a simple software loop. This facility removes the need for a UART in the C without incurring an excessive software overhead. The Tx retiming circuit consists of two 1-bit registers in series, the input of the first is connected to the TXD pin and the output of the second feeds the FSK modulator. The second register is clocked by an internally generated 1200Hz signal and when this occurs the CLK input is sampled. If the CLK input is high the TXD pin directly controls the FSK modulator, if the CLK input is low the FSK modulator is controlled by the output of the second register and the RDY pin is pulled low. The RDY output is reset by a high level on the CLK input pin. A low to high change on the CLK input pin will latch the data from the TXD input pin into the first register ready for transfer to the second register when the internal 1200Hz signal next occurs. To use the retiming option, the CLK input should be held low until the RDY output is pulled low. When the RDY pin goes low, the next data bit should be applied to the TXD input and the CLK input pulled high and then low within the time limits defined in Figure 9.
FSK Modulator input : RDY output : CLK input : TXD input :
1
1
2
3
tR
2 3 4
RDY
tD tcHI
CLK
tS tH 1
TXD
tD = Internal MX604 delay; tR = low to CLK going low; tS = data set up time tcHI = CLK high time, tH = data hold time
Figure 9: FSK Operation with Tx Data Retiming To ensure synchronization between controlling device and the MX604 when entering Tx retiming mode the TXD pin must be held at a constant logic level from when the CLK pin is first pulled low to the end of loading in the second retimed bit. Similarly when exiting Tx retiming mode the TXD pin should be held at the same logic level as the last retimed bit for at least 2 bit times after the CLK line is pulled high.
1998 MXCOM, INC. Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
11
MX604 PRELIMINARY INFORMATION
If the data retiming facility is not required, then the CLK input to the MX604 should be kept high at all times. The asynchronous data to the FSK modulator will then be connected directly to the TXD input pin. This is illustrated in Figure 10 and will also be the case when transmitting 75bps data which has no retime option.
TXD input : FSK Modulator input :
N-2 N-2
N-1 N-1
N N
N+1 N+1
N+2 N+2
Figure 10: FSK Operation without Tx Data Re-timing (CLK always high)
5.
5.1
Application
Line Interface
The signals on the telephone line are not suitable for direct connection to the MX604. A Line Interface circuit is necessary to: Provide high voltage and dc isolation Attenuate the Tx signal present at the Rx input Provide the low impedance drive necessary for the line Filter the Tx and Rx signals
C5
LINE
C R2
A1 RXIN
1:1
0V
B
A2
R2 R3 R4-R7
1998 MXCOM, INC.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
+
Z C6 R4 R5 C7 R6 R3 A
TXOUT VBIAS
See Notes See Notes 100k 1%, 1%, 1%, C5 C6 C7 22F 100pF 330pF 20% 10% 10%
R7
RXAMPOUT
Figure 11: Line Interface Circuit
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MX604 PRELIMINARY INFORMATION
Line Interface Notes: The components 'Z' between points B and C should match the line impedance. Device A2 must be able to drive 'Z' and the line. R2: For optimum results R2 should be set so that the gain is VDD/5.0, i.e. R2 = 100k at VDD = 5.0V, rising to 150k at VDD = 3.3V. R3: The levels in dB (relative to a 775mVRMS signal) at 'A', 'B' and 'C' in the line interface circuit are: 'A' = 20Log(VDD/5) 'B' = 'A' + 20Log(100k/R3) 'C' = 'B' - 6 VDD 3.3V 5.0V 'A' -3.6dB 0dB R3 100k 150k 'B' -3.6dB -3.5dB 'C' -9.6dB -9.5dB
6.
6.1
Performance Specification
Electrical Performance
Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. General Supply (VDD - VSS) Voltage on any pin to VSS Current VDD VSS Any other pins DW / PDIP Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Temperature Xtal Frequency Operating Limits Notes: 1. A crystal frequency of 3.579545MHz 0.1% is required for correct FSK operation. 1 Min. 3.0 -40 3.575965 Max. 5.5 85 3.583125 Units V C MHz -55 -40 800 13 125 85 mW mW/C above 25C C C -30 -30 -20 30 30 20 mA mA mA Min. -0.3 -0.3 Max. 7.0 VDD + 0.3 Units V V
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
13
MX604 PRELIMINARY INFORMATION
Operating Characteristics For the following conditions unless otherwise specified: VDD = 3.3V at TAMB = 25C Xtal Frequency = 3.579545MHz 0.1%, 0dBV corresponds to 1.0VRMS, 0dB = 0dBm = 775mVRMS into 600. Notes DC Parameters IDD (M0='1', M1='1') IDD (M0 or M1='0') at VDD = 3.0V IDD (M0 or M1='0') at VDD= 5.0V Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (VIN = 0 to VDD), Excluding XTAL/CLOCK Input Output Logic '1' Level (lOH = 360A) Output Logic '0' Level (lOL = 360A) Output 'off' State Current (VOUT = VDD) FSK Demodulator Bit Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency Valid Input Level Range Acceptable Twist (Mark Level WRT Space Level) Acceptable Signal to Noise Ratio Level Detector 'On' Threshold Level Level Detector 'Off' to 'On' Time (Figure 4 TeON) Level Detector 'On' to 'Off' Time (Figure 4 TeOFF) FSK Retiming Acceptable Rx Data Rate Tx Data Rate FSK Modulator TXOUT Level Twist (Mark Level WRT Space Level) 1200bps (M1='0', M0='1'). Bit Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency 75bps (M1='0', M0='0'). Bit Rate Mark (Logical 1) Frequency Space (Logical 0) Frequency 0 388 448 75 76 392 452 Baud Hz Hz 0 1297 2097 1200 1212 1303 2103 Baud Hz Hz 5 -1.0 -2.0 0 0 1.0 2.0 dB dB 1188 1194 1200 1212 1206 Baud Baud 8.0 4 3 3 0 1280 2068 -40.0 -7.0 20.0 -40.0 25.0 1200 1300 2100 1212 1320 2132 -8.0 7.0 Baud Hz Hz dBV dB dB dBV ms ms -1.0 VDD-0.4 0.4 1.0 1, 2 1 1 70% 30% 1.0 1 1.0 1.7 1.25 2.5 A mA mA VDD VDD A V V A Min. Typ. Max. Units
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
14
MX604 PRELIMINARY INFORMATION
Notes Input Amplifier Impedance (RXIN Pin) Voltage Gain XTAL/CLOCK Input 'High' Pulse Width 'Low' Pulse Width Operating Characteristics Notes: 7 7 6 6
Min. 10.0
Typ.
Max.
Units M
500 100 100
V/V ns ns
1. Not including any current drawn from the MX604 pins by external circuitry other than X1, C1 and C2. 2. TXD, RXEQ and CLK inputs at VSS, M0 and M1 inputs at VDD. 3. Measured at the Rx Input Amplifier output (pin RXAMPOUT) for 1300Hz and VDD= 5.0V. The internal threshold levels are proportional to VDD. To cater for other supply voltages or different signal level ranges the voltage gain of the Rx Input Amplifier should be adjusted by selecting the appropriate external components as described in section 5.1 4. Flat noise in 300-3400Hz band. 5. Relative to 775mVRMS with VDD= 5.0V for load resistance greater than 40k. 6. Open loop, small signal low frequency measurements. 7. Timing for an external input to the XTAL/CLOCK pin.
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
15
MX604 PRELIMINARY INFORMATION
6.2
Timing
Notes 1, 5 1, 6 2 2 2 3, 4 3, 4 3 4 4 4 1 1 1 1 800 Min. Typ. 2.55 0.1 20 4.0 0.2 1 Max. Units ms ms ms ms ms s s s s s s
Data and Mode Timing Rx Data Delay (RXIN to RXD) Tx Delay Data (TXD to TXOUT) Mode change delay ZP to Tx or Rx Mode change delay Tx1200 to Rx1200 Mode change delay Rx1200 to Tx1200 tD = Internal MX604 delay tcHI = CLK High time tcLO = CLK low time tR = RDY low to CLK going low tS = Data Set-up time tH = Data Hold time Timing Notes 1. When data retiming is not enabled.
2. Delay from mode change to reliable data at TXOUT or RXD pins. 3. Reference Figure 7. 4. Reference Figure 9. 5. Reference Figure 12. 6. Reference Figure 13.
RXIN (FSK Signal) Rx Data Delay RXD
Note: M0 and M1 are preset and stable. Figure 12: RXIN to RXD Delay time
Valid 1 or 0
FLO TXOUT (FSK Signal) TXD
FHI
FLO
FHI
Tx Data Delay
Note: M0 and M1 are preset and stable. FLO and FHI are the two FSK signaling frequencies. Figure 13: TXD to TXOUT Delay time
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
16
MX604 PRELIMINARY INFORMATION
6.3
Packaging
Package Tolerances
A Z B E W L PIN 1 X Y C H J P K T
DIM. A B C E H J K L P T W X Y Z MIN. TYP. MAX.
0.413 (10.49) 0.395 (10.03) 0.299 (7.59) 0.286 (7.26) 0.093 (2.36) 0.105 (2.67) 0.390 (9.90) 0.419 (10.64) 0.003 (0.08) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) 0.041 (1.04) 0.016 (0.41) 0.050 (1.27) 0.050 (1.27) 0.009 (0.23) 0.0125 (0.32) 45 0 10 7 5 5
ALTERNATIVE PIN LOCATION MARKING
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 14: 16-pin SOIC Mechanical Outline: Order as part no. MX604DW
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP . MAX.
0.810 (20.57) 0.740 (18.80) 0.262 (6.63) 0.240 (6.10) 0.135 (3.43) 0.200 (5.06) 0.390 (9.91). 0.300 (7.62) 0.290 (7.37) 0.325 (8.26) 0.015 (0.38) 0.070 (1.77) 0.014 (0.35) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.056 (1.42) 0.064 (1.63) 0.150 (3.81) 0.121 (3.07) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7
B
E1 Y
E
PIN 1
T
K H L J J1 P
C
NOTE: All dimensions in inches (mm.) Angles are in degrees
Figure 15: 16-pin PDIP Mechanical Outline: Order as part no. MX604P
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
17
MX604 PRELIMINARY INFORMATION
A
A B C E H J L P T Y
Package Tolerances
DIM. MIN. TYP. MAX.
ALTERNATIVE PIN LOCATION MARKING
B
E L
PIN 1 Y C H J P
T
0.311 (7.90) 0.303 (7.70) 0.169 (4.30) 0.177 (4.50) ---------0.047 (1.20) 0.248 (6.30) 0.256 (6.50) 0.002 (0.05) 0.006 (0.15) 0.007 (0.17) 0.012 (0.30) 0.020 (0.50) 0.030 (0.75) 0.0256 (0.65) 0.003 (0.08) 0.008 (0.20) 0 8
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 16: 24-pin TSSOP Mechanical outline: Order as part no. MX604TN
1998 MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking On CML Microcircuits (USA) products, the `MX-COM' textual logo is being replaced by a `CML' textual logo.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/2 May 2002

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